Abdul Sami
FPGA Engineer with expertise in RTL design (VHDL/Verilog), simulation, and synthesis, place & route and timing closure on AMD (Xilinx) FPGA and SOC platforms, with experience in FPGA/software co-design and system integration.
- Role
Sr. R&D & FPGA Engineer
- Years of Experience
4 years
Skillsets
- APB
- AXI4
- C
- C++
- I2C
- Mil1553b
- PetaLinux
- Python
- SPI
- SystemVerilog
- UART
- UVM
- Verilog
- VHDL
- Vitis
- Vivado
Professional Summary
4Years
- Apr, 2025 - Present1 yr 1 month
Sr. R&D Engineer
Logic Fruit Technologies - Sep, 2024 - Apr, 2025 7 months
R&D Engineer
Logic Fruit Technologies - Sep, 2023 - Sep, 20241 yr
R&D Engineer-Trainee
Logic Fruit Technologies - Oct, 2021 - Mar, 2022 5 months
FPGA System Design Trainee
PinE Training Academy of VLSI & Embedded - Sep, 2022 - Sep, 20231 yr
Jr. FPGA Engineer
MKU
Work History
4Years
Sr. R&D Engineer
Logic Fruit TechnologiesApr, 2025 - Present1 yr 1 month
R&D Engineer
Logic Fruit TechnologiesSep, 2024 - Apr, 2025 7 months
R&D Engineer-Trainee
Logic Fruit TechnologiesSep, 2023 - Sep, 20241 yr
Define and document system architecture, design, and test plans based on specifications for development. Perform FPGA/SOC board bring-up, pin planning, constraint mapping, developing rtl modules and testbenches, design optimization, and Timing Closure. Perform on-board testing, develop automation scripts for regression/sanity testing, and resolve defects through structured RCA.
Jr. FPGA Engineer
MKUSep, 2022 - Sep, 20231 yr
Developed RTL code and testbenches, integrated modules, and performed functional and timing simulations performed RTL optimization for timing closure, resource utilization, and power efficiency. Verified FPGA functionality on hardware and conducted root cause analysis to debug logic failures and interface-level anomalies.
FPGA System Design Trainee
PinE Training Academy of VLSI & EmbeddedOct, 2021 - Mar, 2022 5 months
Major Projects
6Projects
AMD Video Scaler
Implemented Lanczos and Bilinear algorithms for image upscaling in RTL using Verilog and in HLS using C. Optimized kernel-memory mapping on AI Engine tiles to maximize computation speed and minimize latency, area, and power.
Kria KV260 Bring-Up
Built custom OS using Petalinux and ran the Tensorflow CNN Model for image classification using Vitis-AI. Authored a white paper for the bring-up process.
MIL1533B Demo
Developed bare-metal firmware to demonstrate functionality of the RTL ML1533B IP on a custom board, implementing and validating client-provided test cases for verification.
MIL
Designed and implemented FSM for BC to RT communication, Data Serializer and Deserializer module for MIL1553B protocol. Implemented UART with AXI4 interface having 32 bits address alignment.
Thermal Imager
Implemented image-simulator, 1-point non-uniformity correction module, and raw to RGB module in a real-time image processing pipeline. Designed a human-to-machine module for system interaction.
Optical Weapon Sight
Implemented serial protocols like UART and I2C for interfacing thermal camera and micro-OLED display. Interfaced multi-sensor Ballistic Computer Chip to provide offsets for targeting in real-world scenarios.
Education
FPGA System Design
Pine Training Academy (2022)B.Tech - ECE
Jamia Hamdard University (2022)Class 12th - Science
NIOSClass 10th - Science and Math
New Horizon School