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Vetted Talent

Arun Pradhan

Vetted Talent
Hands on experience in Signal Processing (Audio, Acoustic, Speech, Image and Video, Physical Layer/Wireless-5G NR /CDMA2000 ),computer vision and Machine learning, Deep Learning & IoT aspirant in various domains ,contributed as Individual contributor , Technical leader and Architect. Comprehensive experience on requirement engineering, algorithm development, reference software modelling (fixed point and floating point ),porting, optimisation , validation , release package preparation and integration with various framework on various embedded Architectures (single core, heterogeneous and homogeneous Multi core SoC(VLIW, SIMD / Vectorisation, RISC ) targeted for real time application . Experience in DL interference implementation using TFLM and NN library . Co working with RTL experts for IP /accelerator development in FPGA /ASIC.
  • Role

    Audio Architect, Feature Engineering | Algorithm Engineer

  • Years of Experience

    13.2 years

Skillsets

  • Audio analytics
  • Acoustic algorithms
  • video processing
  • Testing and debugging
  • software optimization
  • mentoring teams
  • Iot architecture
  • Framework Design
  • Digital Health
  • Cross-functional Coordination
  • Biomedical Engineering
  • Deep Learning - 3 Years
  • Dsp software development
  • Physical layer algorithms
  • Wireless standards
  • Signal Processing
  • Machine Learning
  • Image Processing
  • Embedded Systems
  • Algorithm development
  • Computer Vision
  • Deep Learning - 3 Years

Vetted For

9Skills
  • Roles & Skills
  • Results
  • Details
  • icon-skill_image
    Senior Firmware EngineerAI Screening
  • 32%
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  • Skills assessed :Cross-functional collaboration, CI/CD Pipeline, Embedded-C, Embedded Firmware Development, Firmware Testing, IoT, Problem Solving Attitude, Python, Strong Attention to Detail
  • Score: 29/90

Professional Summary

13.2Years
  • Nov, 2024 - Present1 yr 7 months

    Manager -Audio Feature Owner Lead

    Visteon Corporation
  • Mar, 2024 - Nov, 2024 8 months

    Senior Principal Engineer - Audio Specialist

    FEV India Pvt Ltd
  • Jan, 2024 - Jul, 2024 6 months

    Signal Processing Lead

    Paras Defence & Space Technologies Ltd.
  • Dec, 2019 - Oct, 20211 yr 10 months

    Architect (Lead Consultant)

    Nokia Solution Network
  • Nov, 2021 - May, 2022 6 months

    Independent Consultant

    Logitech
  • May, 2022 - Oct, 20231 yr 5 months

    Senior Engineer (Audio Algorithm)

    GOODIX Technology INC.
  • Jun, 2019 - Nov, 2019 5 months

    Consultant

    Innovision (Inceptor Technologies Pvt Ltd)
  • Apr, 2018 - May, 20191 yr 1 month

    Lead Algorithm Engineer

    ThinkLabs LLC
  • Jan, 2016 - Mar, 20182 yr 2 months

    Architect

    Harman Connected Services Pvt. Ltd.
  • Jun, 2013 - Jan, 2014 7 months

    DSP Architect (Consultant)

    Rebaca Technologies Pvt. Ltd.
  • Apr, 2014 - Mar, 2015 11 months

    Senior DSP Architect

    Videonetics Technologies Pvt. Ltd.
  • Apr, 2015 - Jan, 2016 9 months

    R & D Engineer - Expert

    Logic Fruit Technology Pvt. Ltd.
  • Jun, 2012 - May, 2013 11 months

    DSP Architect

    IB Technology

Applications & Tools Known

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    Python

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    OpenCV

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    SDKs

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    ARM

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    CONFLUENCE

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    SVN

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    Azure ML Studio

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    Anaconda

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    PyCharm

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    Labview

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    MS VISIO

Work History

13.2Years

Manager -Audio Feature Owner Lead

Visteon Corporation
Nov, 2024 - Present1 yr 7 months
    Responsible for Audio IP development including specification, algorithm and software development, porting, optimization, integration, tuning, and certification for various performance features. Collaborating with external stakeholders for evaluation and requirements clarification.

Senior Principal Engineer - Audio Specialist

FEV India Pvt Ltd
Mar, 2024 - Nov, 2024 8 months

Signal Processing Lead

Paras Defence & Space Technologies Ltd.
Jan, 2024 - Jul, 2024 6 months
    Led algorithm development, simulation, and performance evaluation for radar signal processing focusing on SAR image formation and ML-based object tracking.

Senior Engineer (Audio Algorithm)

GOODIX Technology INC.
May, 2022 - Oct, 20231 yr 5 months
    Developed audio algorithms and embedded software for automotive platforms, focused on beamforming, noise reduction, and wakeup word detection optimization.

Independent Consultant

Logitech
Nov, 2021 - May, 2022 6 months
    Developed algorithms for beamforming, acoustic echo cancellation, and noise reduction for next-generation large-room video conferencing solutions.

Architect (Lead Consultant)

Nokia Solution Network
Dec, 2019 - Oct, 20211 yr 10 months
    Developed physical layer algorithms and fixed-point models for 5G NR channels. Supported debugging and validation efforts in real-world scenarios.

Consultant

Innovision (Inceptor Technologies Pvt Ltd)
Jun, 2019 - Nov, 2019 5 months
    Worked on the development of embedded DSP software for hearing aids utilizing machine learning and signal processing techniques.

Lead Algorithm Engineer

ThinkLabs LLC
Apr, 2018 - May, 20191 yr 1 month
    Contributed to signal processing and software engineering focused on body sound analytics, digital stethoscope technology, and IoT solutions.

Architect

Harman Connected Services Pvt. Ltd.
Jan, 2016 - Mar, 20182 yr 2 months
    Managed and designed algorithms for engine order cancellation, acoustic feedback integration in car audio systems, and media server enhancements for video conferencing applications.

R & D Engineer - Expert

Logic Fruit Technology Pvt. Ltd.
Apr, 2015 - Jan, 2016 9 months
    Worked as an expert in computer vision applications, contributing algorithms using OpenCV and QT framework for surveillance systems.

Senior DSP Architect

Videonetics Technologies Pvt. Ltd.
Apr, 2014 - Mar, 2015 11 months
    Focused on DSP architecture development for security and surveillance applications.

DSP Architect (Consultant)

Rebaca Technologies Pvt. Ltd.
Jun, 2013 - Jan, 2014 7 months
    Worked on embedded DSP architecture for consumer electronics applications.

DSP Architect

IB Technology
Jun, 2012 - May, 2013 11 months
    Architectural contributions to embedded signal processing projects for industrial clients.

Major Projects

7Projects

Digital Stethoscopes Body Sound Enhancement

    Developed state-of-art algorithm for ambient noise reduction, loudness improvement, and acoustic feedback cancellation for paying back body sound through the speaker; anomaly detection in body sound.

Extendable and Flexible Audio Framework for Automotive Amplifier

    Global Audio Amplifier framework design and demonstration on Multicore SoC (TI-Jacinto), porting and optimisation of HALOSONIC algorithms (EOC-Engine order cancellation, ESS) on NXP SoC/Dirana3, integration of Acoustic Feedback cancellation algorithm with car audio amplifier framework.

Virtual Microscope

    Developed 2D image stitching of large sets (e.g., 100x100) and software development in MATLAB/C/C++ for digital pathology applications.

Video Surveillance Application

    Developed video stitching and object tracking algorithm using advanced methods such as features - SIFT, SURF, HOG, Kalman, and Particle Filters for wide area visual surveillance applications.

Deep Learning-Based Audio Analytic Engine

    Designed and implemented an audio analytic engine that analyses abnormal sound detection, speech, and keyword spotting leveraging ML/DL approaches.

Video Collaboration Endpoint

Nov, 2021 - Apr, 2022 5 months
    Responsible for developing Audio Algorithm advancements (beamforming, ambient noise cancellation, AGC, equalizer) targeting large room video conferencing solutions on a Linux platform.

Next Generation Hearing-Aid

Jun, 2019 - Nov, 2019 5 months
    Worked on developing signal processing algorithm and embedded DSP software for affordable hearing aids leveraging embedded cores.

Education

  • MS in Signal Processing

    NTU (Nanyang Technological University), Singapore
  • Bachelor of Engineering (AMIE) in Electronics and Communication Engineering

    The Institute of Engineers, India
  • B.Sc. in Science

    University of Calcutta
  • Certificate in Computing for Artificial Intelligence and Machine Learning

    IISc
  • Post Graduate Diploma in Digital Health and Imaging

    IISc
  • Post Graduate Diploma in HW Design and System Electronics

    CEDTI, Mohali
  • Certificate in Deep Generative Models

  • Certificate

Certifications

  • Machine Learning of Sensory Signals (Video, Image, Speech, Audio) at Indian Institute of Science (IISc), Electrical Engineering Dept., Bangalore

AI-interview Questions & Answers

I have 20 years of experience in digital signal processing and embedded software design, and I've experienced various platforms, including DSP. I work in the domains of cable electronics, telecommunications, automotive, defense, and security. I work in the areas of audio, acoustic speech, competition, image processing, and physical layer signal processing. I use programming languages C++, MATLAB, and sometimes Python. I love to design embedded systems, implement real-time signal processing algorithms, and integrate them into frameworks to enable applications.

The impact of this video on the system is a critical or noncritical factor for the performance of systems, specifically functional performance and system performance, like latency, throughput, and power efficiency? So, what is that? I cannot answer that. Is it? No, I don't know.

(I'll wait for the rest of the transcript to proceed with the corrections)

Well, architecture should be scalable in terms of it has to be first implemented with the very basic functionalities of the computations that map to the hardware architecture. I mean, the data path, especially the instruction set in top 226. So that in any kind of note code of computation, those are well optimized using the processor's instruction set. And then using those low-level functions, which have already been optimized in the 26, will be called or will be used to develop APIs and the creative flow. Conditional code or control code does not need to be optimized, but we will design to handle the flow for that. You know, all the error reporting and everything are taken care of. And finally, these blocks will be integrated in terms of APIs to create a pipeline. And those sets of APIs have been provided.

Well, in a bit of software development, as I said, it covers, interior, functional timelines in terms of user stories. And, it's easiest to do this in terms of tasks, hence of tasks. And, the task status would be reported in terms of completed or in progress. This is done. And this would be logged to each of your three tasks for testing and debugging. And, those who did peer review by the team members. So, every task needs to have a short-term score to have continuously evolving status, and it should be reviewed in standard meetings, the status and the failure of the blockade. So, this would be some continuous flow of improving, so that it covers all subtask tasks and wishes to complete the whole user stories and the whole functional pipelines.

The red lines would be fast, put before the right, and then right.

I don't understand this code snippet when it tries to do. Is this or What does it mean? I am not familiar with this kind of syntax at

Well, That's our task that we know reviewed because the functional terms as a peer review. This design review, code review, and those would be the test design should come from the other functional type of functional team to, for bot testing and the function of the functional features of other teams. And those would be reviewed by other teams. One team developed features. Other teams would view that, and test designs would come from the other team. And test reports should be viewed by then. This is one aspect I can see. And yes. I think this is one of the things I need to develop across Amazon teams. This would be continuously checked in and using the repo and should be thoroughly tested by the test plan, which is reviewed by the other team. As for the test plan, I need to put on the hardware before putting hardware in place. The complexity of the software needs to be estimated in the simulator or using profiling strategies so that it can fit into the existing memory footprint and cycles. The drivers and processing code also need to be tested first, and then the scheduling code, based on the articles I've read. So, there will be some systematic testing of the software, which is why we integrate it with the hardware. So, yes. It's earlier with the approach. It will be taken care of.

Well, we can imply that we can compress the binaries of embedded code from where it needs to be compressed using some HVD. And, while putting out the need to be decompressed, error check, like quality check, SCS, you know, with before after it completes this. And then it adds it to bring it to the memory of the device.