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ARUN RAJ M

FPGA Engineer by profession, signal whisperer by passion.

I spend my days convincing RTL code to behave and my nights wondering why simulations pass but hardware disagrees.

I’ve worked on cool stuff like bad pixel correction, X-band radar and protocols like UART and I2C (basically, I make chips talk politely to each other).

  • Role

    FPGA Engineer

  • Years of Experience

    4 years

Skillsets

  • UART
  • Perl
  • Python
  • Perl
  • Questasim
  • Python
  • SVA
  • Questasim
  • SystemVerilog
  • SVA
  • UART
  • SystemVerilog
  • UVM
  • NCSIM
  • VCS
  • UVM
  • Verilog
  • VCS
  • VHDL
  • Verilog
  • Vivado
  • VHDL
  • Windows
  • Vivado
  • Windows
  • Github
  • APB
  • AXI
  • AXI
  • Coverage-driven verification
  • coverage
  • Crontab
  • Crontab
  • Ctag
  • Ctag
  • Git
  • Git
  • Github
  • AHB
  • Gvim
  • Gvim
  • I2C
  • I2C
  • Linux
  • Linux
  • Makefile
  • Makefile
  • Meld
  • Meld
  • NCSIM

Professional Summary

4Years
  • Jun, 2024 - May, 2025 11 months

    FPGA Engineer

    Marine Electricals
  • Jul, 2023 - Jun, 2024 11 months

    Post Graduate Engineer Trainee Design & Verification Team

    Tata Advanced Systems
  • Jul, 2023 - Jun, 2024 11 months

    Post Graduate Engineer Trainee Design & Verification Team

    Tata Advanced Systems
  • Jun, 2019 - May, 20211 yr 11 months

    Design and Verification Engineer

    MasterVLSI
  • Jul, 2022 - Dec, 2022 5 months

    Project Trainee Internship Design and Verification Team

    Data Patterns
  • Jul, 2022 - Dec, 2022 5 months

    Project Trainee Internship Design and Verification Team

    Data Patterns
  • Jun, 2019 - May, 20211 yr 11 months

    Design and Verification Engineer

    MasterVLSI

Work History

4Years

FPGA Engineer

Marine Electricals
Jun, 2024 - May, 2025 11 months
    Developed a test plan and test cases for IP; performed read and write tests, toggle coverage, and assertion-based verification. Debugged and resolved issues during verification, enhancing overall system stability. Understood protocol behavior, timing requirements, and bus transaction flow.

Post Graduate Engineer Trainee Design & Verification Team

Tata Advanced Systems
Jul, 2023 - Jun, 2024 11 months
    Created test plans and scenarios to validate AXI stream IP functionality through read and write operations. Applied assertion-based verification and monitored toggle coverage metrics. Understood protocol behavior, timing requirements, and bus transaction flow.

Post Graduate Engineer Trainee Design & Verification Team

Tata Advanced Systems
Jul, 2023 - Jun, 2024 11 months

Project Trainee Internship Design and Verification Team

Data Patterns
Jul, 2022 - Dec, 2022 5 months

Project Trainee Internship Design and Verification Team

Data Patterns
Jul, 2022 - Dec, 2022 5 months
    Worked as a project trainee in the Design and Verification Team, supporting verification activities and learning protocol behaviors.

Design and Verification Engineer

MasterVLSI
Jun, 2019 - May, 20211 yr 11 months

Design and Verification Engineer

MasterVLSI
Jun, 2019 - May, 20211 yr 11 months
    Analyzed APB Verification IP compliant with AMBA APB 2.0/3.0 specifications. Designed UVM components including sequencer, driver, monitor, agent. Gained hands-on experience in UVM methodology and SystemVerilog for functional verification. Developed testbenches for PCIe PHY and AXI protocols, and designed key UVM components for AHB protocol.

Major Projects

9Projects

AHB Protocol Development Using UVM

    Designed UVM components such as sequencer, driver, monitor, agent, scoreboard, and environment to simulate AHB bus behavior. Created layered test sequences for varied scenarios and practiced coverage analysis to improve test efficiency.

AHB Protocol Development Using UVM

    Designed key UVM components such as sequencer, driver, monitor, agent, scoreboard, and environment to simulate AHB bus behavior. Created layered test sequences for varied scenarios including single/burst transfers and priority arbitration. Practiced coverage analysis and applied metrics to improve test efficiency and coverage closure.

X-BAND - SoC Based Project

Jun, 2024 - May, 2025 11 months
    Developed a test plan and test cases for IP; performed read and write tests, toggle coverage, and assertion-based verification. Debugged and resolved issues during verification, enhancing overall system stability. Understood protocol behavior, timing requirements, and bus transaction flow.

BadPixel_Correction - IP Design & Verification Based Project

Jul, 2023 - Jun, 2024 11 months
    Created test plans and scenarios to validate AXI stream IP functionality through read and write operations. Applied assertion-based verification and monitored toggle coverage metrics. Understood protocol behavior, timing requirements, and bus transaction flow.

PCI-e(PHY) Protocol

Jun, 2019 - May, 20211 yr 11 months
    Developed a testbench to validate the Physical Layer (PHY) functionality of the PCI Express protocol. Gained knowledge of PCI Express PHY architecture, signaling, encoding, and link training mechanisms.

AXI Protocol Development Using SVM

Jun, 2019 - May, 20211 yr 11 months
    Developed a testbench environment using object-oriented programming in SystemVerilog. Created test scenarios to verify master-slave interactions, arbitration, and transfer priority logic. Collected and analyzed assertions for verification completeness.

APB Protocol Development Using UVM

Jun, 2019 - May, 20211 yr 11 months
    Analyzed APB Verification IP compliant with AMBA APB 2.0/3.0 specifications. Designed UVM components including sequencer, driver, monitor, agent. Gained hands-on experience in UVM methodology and SystemVerilog for functional verification.

PCI-e(PHY) Protocol

Jun, 2019 - May, 20211 yr 11 months
    Developed testbench to validate the Physical Layer (PHY) functionality of the PCI Express (PCIe) protocol. Gained knowledge of PCI Express PHY architecture, signaling, encoding, and link training mechanisms.

AXI Protocol Development Using SVM

Jun, 2019 - May, 20211 yr 11 months
    Created testbench environment using object-oriented programming in SystemVerilog. Developed test scenarios to verify master-slave interactions, arbitration, and transfer priority logic. Collected and analyzed assertions to ensure completeness and robustness of the verification.

Education

  • M.Tech, Defence Electronics System (ECE)

    Defence Institute of Advanced Technology (2023)

  • B.E, Electronics and Instrumentation Engineering

    Saveetha Engineering College (2018)

  • 12th Grade

    Kaligi Ranganathan Montford M.H.S.S (2014)

  • 10th Grade

    Kaligi Ranganathan Montford M.H.S.S (2012)