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Ashutosh Parkhi

With a robust background in software solutions for hardware device mapping, my role as an Engineering Lead at Arm involves leading one of the PyTorch compiler teams to enhance machine learning model performance. Our contributions, crucial to the open source ecosystem of PyTorch empower developers to achieve optimized machine learning implementations.

Previously, as a Staff Compiler Engineer, I was committed to the TVM apache project, integrating neural network libraries and backend compilers, which enabled efficient heterogeneous execution across devices. The collaborative efforts of our team ensure groundbreaking strides in AI tooling and device backend enablement.

  • Role

    staff compiler engineer

  • Years of Experience

    15.42 years

Skillsets

  • Algorithms
  • C
  • C++
  • Data Structures
  • Debugging
  • Linux
  • Perl
  • Python

Professional Summary

15.42Years
  • Mar, 2024 - Jan, 2025 10 months

    Engineering Lead

    Arm
  • Jun, 2023 - Feb, 2024 8 months

    Technical Team Lead

    Arm
  • May, 2021 - May, 20232 yr

    Staff Compiler Engineer

    Arm
  • Jun, 2007 - Jul, 20103 yr 1 month

    Senior Member Technical Staff

    Mentor Graphics
  • Jun, 2012 - Nov, 20175 yr 5 months

    Simulation/Modeling Engineer

    Intel
  • Nov, 2017 - Apr, 20213 yr 5 months

    Senior Software Engineer

    Imagination Technologies

Work History

15.42Years

Engineering Lead

Arm
Mar, 2024 - Jan, 2025 10 months

Technical Team Lead

Arm
Jun, 2023 - Feb, 2024 8 months

Staff Compiler Engineer

Arm
May, 2021 - May, 20232 yr
    Contributed to integration and maintenance of several neural network (NN) software libraries and backend compilers. Enabled efficient heterogeneous execution across multiple devices using TVM.

Senior Software Engineer

Imagination Technologies
Nov, 2017 - Apr, 20213 yr 5 months
    Developed Tensorflow equivalents for network partitioning, graph transforms, and quantization tools in TVM. Designed heterogeneous flow in NNVM to support GPUs and neural network accelerators.

Simulation/Modeling Engineer

Intel
Jun, 2012 - Nov, 20175 yr 5 months
    Developed functional simulation models for media accelerators. Brought up a face recognition application on integrated CPU-GPU simulation systems. Developed SystemC/TLM2 models for neural networks accelerators.

Senior Member Technical Staff

Mentor Graphics
Jun, 2007 - Jul, 20103 yr 1 month
    Developed TCL/TK UI for editing RTL signal combinations post Veloce emulation. Designed converters for Veloce to debussy/vcd trace formats for standardized signal viewing.

Education

  • Masters in Technology (M.Tech/M.E)

    University of Michigan, US (2012)
  • Bachelors of Law (B.L/L.L.B)

    Indian Institute of Technology (IIT BHU), Varanasi (2007)