Kannan S

Developed RTL designs for embedded industrial devices using FPGAs and CPLDs. Designed Verilog/VHDL modules for data acquisition, sensor interface, PWM generation, and signal filtering. Integrated digital designs with microcontroller systems (ARM-based), ensuring robust hardware/software interfacing. Collaborated closely with software and firmware teams throughout project lifecycles to align FPGA interfaces, protocols, and timing requirements. Managed entire FPGA lifecycle: simulation (ModelSim), synthesis, timing closure (Vivado/Quartus), in-system testing (ILA, SignalTap). Performed reverse engineering of legacy FPGA designs and hardware modules to analyze functionality and enable upgrades and integration with modern systems. Optimized logic utilization and latency across multiple devices, improving performance in critical applications. Wrote technical documentation for regulatory submissions (FDA, CE), including test plans and traceability matrices. Key Contributions: Reduced board space by transitioning from discrete logic to compact CPLD-based modules for signal conditioning.