Putluru bhuvaneswari

Worked on automation of generation of table with product L2, weekly list of Jiras as headers. Worked on generation of table with assignee, list of Jiras as headers.

Worked on RTM2HAPS Project where RTM has python script which generates RTL Logic with different seed and is supported in VCS. This RTM needs to be integrated in HAPS. Analyzed and validated the Intel reported JIRAs on GUI of Protocompiler. Worked on feature testing Add_Vivado_IP in Synplify_Premier, Protocompiler. Worked on Denvar project to check features of Synplify are passing the Unified Compile flow when UC2 switch is enabled.

Worked on creating small test-case on HAPS Prototyping tools like ProtoSynthesis, ProtoCompiler. Worked on creating small test-case on Identify. Developed squish testcases on JIRA issues and added to regression framework where squish background mode works on TCL. Developed GUI Interactive attribute examples in Synplify_pro using .xml & .html. Debugging the failures and errors from regression runs. Knowledge on FPGA flow used in Synplify Pro. Trained on VCS simulator for verification and debugging designs. Implemented digital circuits using Xilinx FPGA Architecture like Virtex7. Created testcases using Compiler directives, Attributes and understood their impact on Synthesis Process. Performed Manual Testing on Protosynthesis, Protocompiler, Basic flow Testing and triggered squish regression on Synthesis tools like Synplify, Synplify_pro, Synplify_premier and Synplifypremier_Dp. Triggered squish regression on Debugger tool. Validated the Synplify_pro tool by manual OEM testprocedure and triggered squish runs on six OEMs for every release.