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Rohit Choubey

I am an Application Specific Integrated Circuit (ASIC) Design Engineer with expertise spanning digital design, hardware design, layout design, and design verification, enabling me to contribute across the complete chip development lifecycle.

  • Role

    FPGA engineer

  • Years of Experience

    2.9 years

Skillsets

  • System Verilog
  • On-board debugging
  • synthesis
  • Routing
  • Placement
  • Partitioning
  • Floor Planning
  • Verilog
  • UART
  • AXI
  • STA
  • Simulation
  • RTL
  • IP verification
  • FPGA prototyping
  • FPGA
  • Digital Logic
  • CMOS

Professional Summary

2.9Years
  • Jun, 2024 - Feb, 2025 8 months

    Formal Verification Engineer

    META VLSI
  • Dec, 2022 - May, 20241 yr 5 months

    RTL Design and FPGA Engineer (Research Associate Project Staff)

    IIIT Bangalore
  • Sep, 2022 - Apr, 2023 7 months

    RTL Design & Verification Trainee

    Maven Silicon
  • Jul, 2021 - Jun, 2022 11 months

    Design Engineer Intern Test and Verification

    Ericsson India
  • Aug, 2022 - Nov, 2022 3 months

    RTL Design Engineer

    BITSILICA

Work History

2.9Years

Formal Verification Engineer

META VLSI
Jun, 2024 - Feb, 2025 8 months
    Working as a Formal Verification Engineer for a Samsung client. Performing AXI design and verification using assertion-based methods. Developing and automating verification processes using Python scripting.

RTL Design and FPGA Engineer (Research Associate Project Staff)

IIIT Bangalore
Dec, 2022 - May, 20241 yr 5 months
    Tested various IPs of the 5G NR PDCCH and PUCCH chains. Designing and implementing RTL modules based on project specifications. Collaborating with cross-functional teams to ensure seamless hardware-software integration. Debugging and validating FPGA designs using simulation tools and hardware debugging tools like ILA or Chip Scope. Optimizing designs for timing, area, and power constraints. Developing test benches and verification strategies to ensure functionality and performance. Participating in the bring-up and integration of FPGA-based systems in hardware environments.

RTL Design & Verification Trainee

Maven Silicon
Sep, 2022 - Apr, 2023 7 months
    Training in Digital Design, STA, Verilog, CMOS Design.

RTL Design Engineer

BITSILICA
Aug, 2022 - Nov, 2022 3 months
    Designed and implemented AXI protocol in Verilog. Designed and implemented FIR filter in Verilog. Gained hands-on experience in RTL design and digital logic implementation.

Design Engineer Intern Test and Verification

Ericsson India
Jul, 2021 - Jun, 2022 11 months
    Worked on LUVA LSV automation tasks in the Ericsson Charging Team. Installed AIR/AF on virtual and bare metal (hardware) environments. Upgraded software versions from old to new drops. Conducted sanity and dimensioning tests on 112 test cases and analyzed logs for verification.

Education

  • M.Tech: VLSI Design

    Thapar Institute of Engineering & Technology

  • BE: ECE

    Rajiv Gandhi Proudyogiki Vishwavidyalaya