Shwet dhameliya
working on Al accelerators with strong understanding in implementing its architectural design.Al architecture. Proficient in Verilog, with good understanding of timing analysis and clock domain crossing. Applied skills in implementing Al solutions on Jetson Nano for robotic arm projects during an impactful internship at Einfochips. Well-versed in Robot Operating System (ROS) and proficient in Python. Committed to pushing the boundaries of Al hardware.
- Role
FPGA engineer
- Years of Experience
3 years
- Professional Portfolio
View here
Skillsets
- Oop
- FPGA
- CMOS
- RTL
- ASIC
- Computer architecture vlsi
- Ros(robot operating system)
- ARM assembly
- Verilog hdl
- UART
- Public Speaking
- Data Processing
- Leadership
- I2C
- HPC
- C/C++
- ARM
- Verilog - 1 Years
- Python
- automation
- Design
- On
Professional Summary
3Years
- Oct, 2024 - Present1 yr 6 months
RTL Design Engineer
VICHARAK (A HARDWARE COMPANY) - Aug, 2024 - Present1 yr 8 months
Project Engineer in VLSI-DAC
C-DAC (Center for development of advance computing ) - Oct, 2023 - Aug, 2024 10 months
FPGA Engineer
Vicharak Computers Pvt. Ltd. Summer Intern
GARIMA SYSTEM SOLUTIONS PVT. LTD.- Jan, 2023 - Sep, 2023 8 months
Research and Development Intern
E-Infochips
Applications & Tools Known
GitHub
VS Code
Quartus Prime
Linux
Windows
Arduino
Work History
3Years
RTL Design Engineer
VICHARAK (A HARDWARE COMPANY)Oct, 2024 - Present1 yr 6 months
Project Engineer in VLSI-DAC
C-DAC (Center for development of advance computing )Aug, 2024 - Present1 yr 8 months
Prototyping on Xilinx Virtex ultrascale FPGA for AI accelerated chips. Debugging the DMA/Bridge subsytem for PCIe.
FPGA Engineer
Vicharak Computers Pvt. Ltd.Oct, 2023 - Aug, 2024 10 months
Design micro-architecture and optimization of memory controller for DDR3, deep learning models for image classification (Vgg16) and object detection (mobilenetssd2) tailored for FPGA, leveraging state-of-the-art neural network architectures. Creating efficient and scalable models, enhancing performance for various AI-driven tasks. Engineered FPGA-accelerated solutions for deep learning, aligning hardware design with the unique requirements of neural network computations. Built Industry-standard UART, I2C, MIPI DSI (for cpu-fpga link) and AMBA: APB/AHB/AXI modules to integrate with state of art CNN models and Memory Controller for DDR3. Designed high-performance multipliers for AI Accelerators. Have good practical knowledge of timing analysis and clock domain crossing. Tested designs using Debugger and Analyser. Tech-stack: AI acceleration on FPGA, Linux, Verilator, Python, Icarus Verilog, Efinity, Quartus Prime.
Research and Development Intern
E-InfochipsJan, 2023 - Sep, 2023 8 months
Worked on robotic arm based on Nvidia Jetson Nano. Established robust communication between ROS Nodes. Optimized data processing pipelines. Created end-to-end framework in Client Server Model. Implemented pilot project for mobile automation using object detection (YOLO v3) algorithm. Tech-stack: Python, opencv, ROS(Robot operating System), YOLO v3.
Summer Intern
GARIMA SYSTEM SOLUTIONS PVT. LTD.Worked on Number Plate Detection project. Built a Deep Learning Model in Tensorflow to categorize various number plate patterns.
Major Projects
3Projects
Number Plate Recognition
Created an image classification model from scratch and deployed on web via flask
Automatic railway gate controller
Developed an Automatic Railway Gate Controller project leveraging Arduino as the microcontroller platform and incorporating infrared (IR) proximity sensors for precise train detection. The system, designed to enhance railway safety, autonomously controls the opening and closing of the railway gate based on real-time inputs from the IR sensors. The Arduino microcontroller interprets the sensor data, triggering a motor control system, specifically employing a servo motor, to automate the gates movement.
VERILOG &PYTHON
Education
Bachelor of Technology in Electronics and Communication Engineering
Birla Vishwakarma Mahavidhalaya (2023)