Vikal Chandra

Working on Gigabit Transceiver IP FPGA Prototyping Microarchitecture PCIE Protocol (Link Training) RTL Coding, Debugging, Simulation.

Developed RTL and C code for video processing (rotation, CLAHE, enhancement, stabilization) and memory subsystems with cache and DDR3 integration. Performed CDC analysis using Spyglass CDC; resolved multi-clock domain issues with synchronizers and handshakes. Conducted Lint checks via Spyglass Lint to ensure clean RTLeliminated latches, loops, and unreachable states. Defined XDC constraints and executed STA in Vivado to meet timing at synthesis and implementation. Worked on Xilinx Artix-7 and Zynq-7000 SoCs; implemented AXI4 Master, Slave, and Interconnect IPs. Built Vitis C applications and test plans for RTL and FPGA-level validation. Applied synthesis strategies and timing-driven place-and-route for optimal FPGA performance.

Developed RTL for protocol modules including I2C, SPI, UART, FlexRay, and CXPI for integration into Keysights Infiniivision Oscilloscopes. Conducted Lint and CDC analysis, rectifying structural and clock domain issues during emulation and synthesis phases. Performed comprehensive STA using Synopsys Design Compiler, verifying setup, hold, and clock uncertainty margins. Conducted functional and timing simulations, signal tracing, and waveform debugging for protocol decoding accuracy.

Designed AXI, APB, and AHB protocol interfaces and bridges for seamless memory and peripheral communication. Authored clean and lint-free RTL code adhering to company-specific coding guidelines. Written assertions, and functional coverage points for comprehensive verification. Performed CDC analysis on data crossing boundaries between different clock domains.

Serial Adder Design Implemented using Verilog and SystemVerilog. APB Memory Design Designed RTL for a 1Kx32 APB protocol-based memory and developed a testbench for verification. Hands-on experience in ASIC, FPGA, and SoC Design, including RTL coding, testbench development, verification, and debugging.