• Founded in

    2008

  • Company Industry

    Semiconductors

  • Headquarters

    No-1216 & 17, 2nd Floor, 24th Main, HSR Sector -1, Bangalore, - 560102, Karnataka, IN

About us

ARF is a leading Analog/RF mixed signal layout design solutions company with a world-wide customer base including many Tier-1 accounts. We provide IC Layout Design of Analog, Mixed signal, IOs , Standard Cell Libraries/SRAM and High-Speed Interfaces/SerDes/PHYs from Module level to full chip level integration and backend verification. Core Expertise: High-Speed Design Layout (56/112G), SerDes/PHYs, IOs, Custom SRAM, BiCMOS, SiGe Process Node: 180nm to 5nm at leading foundries Flexible Business model to offer Layout services both on-site/off-site. ODC model setup at leading Chip/IP Companies Our Commitment: Fastest design to tapeout time with quality deliverables

Funding

Self-funded (bootstrapped) company without external investments.

Current Openings at ARF Design

Senior Physical design Engineer

7 - 15 Years ExpOnsite - Bengaluru
DesignPhysical DesignSemiconductorTiming Closure

ASIC Design verification

7 - 10 Years ExpOnsite - Bengaluru
functional coveragecode coverageFormal Verificationassertion-based verificationUVM MethodologyModular Testbenchconfigurable IP DV

Circuit Design Engineer

5 - 7 Years ExpOnsite - Bengaluru
Circuit designpower managementADCDACsimulation tools

Analog Layout Design Engineer

2 - 7 Years ExpOnsite - Bengaluru
Semiconductoranalog layoutRF LayoutSTD Cell LayoutMemory LayoutIC Layout

Analog Circuit Design Engineer

4 - 7 Years ExpOnsite - Bengaluru
DesigncircuitscircuitCMOSTransistorSPICELayout

Analog Layout Engineer

3 - 5 Years ExpOnsite - Bengaluru
LayoutDesign

RTL design verification /ASIC design verification

5 - 10 Years ExpOnsite - Bengaluru
RTL_Design_verificationVerilogsystemverilogASIC design

RTL Design verification Engineer

5 - 10 Years ExpOnsite - Bengaluru
RTL designverificationVerilogsystemverilogOVMUVMASIC design

Physical Design Engineer

5 - 10 Years ExpOnsite - Bengaluru
DesignSemiconductoradmP&RPhysical Designsynthesis

Analog Design Engineer

5 - 20 Years ExpOnsite - Bengaluru
Designcircuitstransistor-levelSPICELayoutmodelsPVT

RTL Design Verification

5 - 10 Years ExpOnsite - Bengaluru
RTL designVerilogsystemverilogASIC designverification methodologiesProblem SolvingDebugging

RTL Design Verification

5 - 10 Years ExpOnsite - Bengaluru
VerilogsystemverilogRTL designdesign verificationOVMUVMASIC design

Design verification Engineer

5 - 15 Years ExpOnsite - Bengaluru
VerilogsystemverilogASIC designverification methodologiesSemiconductorRTL_Design_verification

Senior physical Design Engineer

5 Years ExpOnsite - Bengaluru
Physical DesignsynthesisSemiconductorP&RTiming Closure

Circuit Design Engineer

5 - 10 Years ExpOnsite - Bengaluru
AnalogMixed SignalDesigncircuitsSPICECMOSTransistor

Circuit Design Engineer

5 - 20 Years ExpOnsite - Bengaluru
DesigncircuitCMOSadcs

Design verification Engineer

5 - 15 Years ExpOnsite - Bengaluru
VerilogRTL designUVMASIC designverification

Design verification Engineer

5 - 20 Years ExpOnsite - Bengaluru
VerilogSystem VerilogRTL designOVMUVMASIC designVerification Techniques

Physical Design Engineer

5 - 10 Years ExpOnsite - Bengaluru
Physical DesignSemiconductorECOclock-tree synthesispower-aware PDPD-STATiming Closure

Design verification Engineer

5 - 20 Years ExpOnsite - Khordha
VerilogSystem VerilogRTL designOVMUVMASICverification

Physical Design Engineer

5 - 15 Years ExpOnsite - Khordha
Physical DesignSemiconductorP&RadmVLSI designsemiconductor device

Design verification Engineer

5 - 20 Years ExpOnsite - Khordha
VerilogSystem VerilogRTL designASIC designOVMUVM

Senior Physical Design Engineer

5 - 20 Years ExpOnsite - Bengaluru
Physical DesignSemiconductorECOsynthesisPD-STApower-aware

Analog Layout Design Engineer

2 - 10 Years ExpOnsite - Bengaluru
LayoutDesignIOVirtuosoESDlower NodeAnalog

Design Verification Engineer

5 - 20 Years ExpOnsite - Bengaluru
VerilogSystem VerilogOVMUVMASIC designVerification TechniquesDebugging

Physical Design Engineer

5 - 15 Years ExpOnsite - Bengaluru
Physical DesignSemiconductorclock-tree synthesispower-aware PDPD-STATiming Closure

Analog Layout Engineer

3 - 10 Years ExpOnsite - Bengaluru
LayoutDesignVLSI designLVSDRCsemiconductor device

Senior Design verification Engineer

5 - 20 Years ExpOnsite - Bengaluru
VerilogSystem VerilogASIC designDebugging

Physical Design Engineer

5 - 15 Years ExpOnsite - Khordha
Physical DesignSemiconductoradmP&RVLSI designECO

Physical design Engineer (PD)

5 - 20 Years ExpOnsite - Bengaluru
Physical DesignECOclock-treePD life cyclepower-awarePD-STAtiming

RTL Design Verification Engineer

5 - 15 Years ExpOnsite - Bengaluru
RTL verificationUVMSystem VerilogDVDesignVerilogip

Senior Circuit Design Engineer

5 - 20 Years ExpOnsite - Bengaluru
Analog circuitDDRMIPIPCIeVerilogDesigncircuits

Analog Circuit Design Engineer

4 - 20 Years ExpOnsite - Bengaluru
RLC circuitsCMOS DevicesCadence Virtuosospice simulatorsDigital DesignCircuit designtransistor-level

Design Verification Engineer

5 Years ExpOnsite - Bengaluru
VerilogSystem VerilogOVMUVMASIC designVerification Techniques

Physical Design Engineer

5 - 20 Years ExpOnsite - Bengaluru
Physical DesignSemiconductorECOsynthesispower-awarePD-STATiming Closure

Physical Design Engineer

5 - 15 Years ExpOnsite - Bengaluru
clock-tree synthesispower-aware PDPD-STAtiming constraintsTiming Closuretapeout cyclesPD life-cycle

Analog Mixed Signal Designer

5 - 20 Years ExpOnsite - Bengaluru
CMOS DevicesCadence Virtuosospice simulatorsAnalog circuit designVerilogRLC circuitsdigital building blocks

Design Verification Lead

4 - 12 Years ExpOnsite - Bengaluru
RTL verificationUVMOVMVMMSystem VerilogPCI-EHBM

Analog Mixed Signal Designer

1 - 10 Years ExpOnsite - Bengaluru
CMOS Devicescustom designSPICE SimulationsVerilogperformance characterizationanalog mixed signaltransistor-level design

Physical Design Engineer

6 - 20 Years ExpOnsite - Bengaluru
Tape OutDesignclock-tree synthesistiming constraintsECO life cyclepower-awarePD-STA

Design Verification Engineer

3 - 20 Years ExpOnsite - Bengaluru
UVMSystem VerilogAssertion verificationfunctional coveragePCI-EUCIeHBM

Senior Physical Design Engineer

5 - 20 Years ExpOnsite - Bengaluru
Physical DesignTape Outclock-tree synthesispower-awareTiming ClosurePD life cycleECO life cycle

RTL Design Engineer

3 - 10 Years ExpOnsite - Bengaluru
RTL designVerilogVhdlEDA toolssynthesisPythonlow power design

Senior Physical Design Engineer

5 - 15 Years ExpOnsite - Bengaluru
Tape Outclock-tree synthesispower-aware PDTiming ClosurePD life cyclePD-STA

Physical Design Engineer

6 - 20 Years ExpOnsite - Bengaluru
Physical Designadmpower-aware PD

Design Verification Lead

6 - 12 Years ExpOnsite - Bengaluru
RTL verificationUVMOVMSystem Verilogassertion-based verificationHBMPCI-E

Physical Design Engineer /PD Engineer

5 - 20 Years ExpOnsite - Bengaluru
Physical DesignDesignECOTiming Closureadmpower-awareclock-tree

Physical Design Engineer /PD Engineer

3 - 15 Years ExpOnsite - Bengaluru
Physical Designtiming constraintsClosureadmclock-tree synthesis

Analog Circuit Design Engineer

4 - 20 Years ExpOnsite - Bengaluru
DesignDigitaladcscircuitcustom designcircuits