About
PricingContact
  • Company Industry

    Semiconductor Manufacturing

  • Headquarters

    5488 Marvell Lane, Santa Clara, - 95054, CA, US

About us

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

Funding

Self-funded (bootstrapped) company without external investments.

Current Openings at Marvell Technology

Principal validation Engineer

10 Years ExpOnsite - Bengaluru
C/C++ARM assemblySSDFirmwareDebuggingNANDPCIE

Sr. Staff Field Applications Engineer(Switching)

8 - 12 Years ExpOnsite - Bengaluru
CC++DebuggingNetworkingL2 switchingRoutingLinux

IP Physical Design Engineer

10 - 25 Years ExpOnsite - Bengaluru
Physical DesignRTLGDSIIsynthesisplace and routeTiming Closurestatic timing

Senior Principal Physical Design Engineer

18 - 25 Years ExpOnsite - Bengaluru
Physical DesignRTL synthesisDFTtimingScriptingSOCautomation

Full-Chip Principal Physical Design Engineer

10 - 18 Years ExpOnsite - Bengaluru
Physical DesignRTLGDSScriptingTCLPerlPython

Senior Principal Design Verification Engineer

18 Years ExpOnsite - Bengaluru
design verificationUVMCARMAMBADDREthernet

Senior Staff Engineer Design Verification

8 - 12 Years ExpOnsite - Bengaluru
SystemVerilogUVMASIC verificationDigital DesignDebug toolsAMBA protocolsTest Planning

Chip Lead

16 Years ExpOnsite - Bengaluru
RTL designverificationPhysical DesignScriptingEDA toolsArchitectureDatacenter

Principal Design Engineer

12 - 17 Years ExpOnsite - Bengaluru
SoC ArchitectureVerilogVHDLPythonSdramMemory controllersPCIE

Principal Design Verification Engineer

12 - 17 Years ExpOnsite - Bengaluru
SoC architecturesSystem VerilogUVMASIC verificationDigital DesignDebug toolsAMBA protocols

Timing & Power Analysis CAD Engineer

6 - 10 Years ExpOnsite - Bengaluru
power analysisTCL scriptingPrimetimePrimePowerSTAhierarchical designsautomation

Staff Physical Verification CAD engineer

5 - 10 Years ExpOnsite - Bengaluru
CADEDAPythonTCLCalibreICVMentor Graphics

Principal Engineer, Subsystem CoE Emulation

10 - 15 Years ExpOnsite - Bengaluru
SOC emulationvalidationDebughigh-speed protocolsemulation platformsScriptingMemory interfaces

Sr. Staff RTL Design Engineer - PCIe

8 Years ExpRemote - Bengaluru
RTL designSystemVerilogVerilogPCIECXLARMEDA tools

Staff CAD Engineer (Power Signal Integrity)

6 Years ExpOnsite - Bengaluru
EM analysisIR analysisCadence VoltusPower Signal IntegrityTCLPython

Sr. Principal Engineer, RTL ASIC Design

18 Years ExpOnsite - Hyderabad
ASIC designSoC ArchitectureRTL codingPerformance AnalysisDigital DesignARM Architecture

Senior Staff- IP RTL Design Engineer

8 - 14 Years ExpOnsite - Bengaluru
RTL designUCIeHBMSystemVerilogVerilogCDC/RDCSoC Architecture

Senior Principal Engineer - Verification / AMS / SerDes

17 Years ExpOnsite - Bengaluru
verificationSerdesAMSSystemVerilogUVMGLS

Senior Staff/Principal SQA Engineer (Firmware/Embedded Testing, C/C++, Python/Bash)

7 - 15 Years ExpOnsite - Hyderabad
PythonC/C++BashFirmwareembeddedHardwareDebugging

Principal Validation Engineer

5 - 10 Years ExpOnsite - Pune
LinuxembeddedC/C++DDR

Senior Staff Validation Engineer

FreshersOnsite - Bengaluru
C/C++ARM assembly64 bit Arm CPUFirmwareDebuggingSSDNAND

Senior Principal Engineer - RTL

20 Years ExpOnsite - Bengaluru
RTLVerilogSystem VerilogASICAIPythonIP integration

Senior Staff Engineer - AMS IP Verification

8 - 12 Years ExpOnsite - Bengaluru
SystemVerilogUVMSerdesAMSverificationFirmware

Senior Principal Engineer, RTL ASIC Design

18 Years ExpOnsite - Bengaluru
RTLASIC designPythonTCLShellC++EDA tools

Frontend Infrastructure CAD/Tools Engineer

5 Years ExpOnsite - Bengaluru
PythonPerlEDA toolsGitGithubAI integrationLLM

Senior Staff Verification Engineer

8 Years ExpOnsite - Pune
SystemVerilogHDLUVMARM M series ProcessorsPerlShellPython

Principal Engineer (L2, L3 Protocol Development, Switching/Routing)

8 - 15 Years ExpOnsite - Bengaluru
C/C++PythonEthernet SwitchingRouting ProtocolsEmbedded SystemsLinuxnetwork software

Principal SQA Engineer (L2, L3, Python Automation)

10 - 20 Years ExpOnsite - Bengaluru
PythonL2/L3NetworkingQA methodologiesTest PlanningLinux/UnixTraffic generators

Staff/ Senior Staff QA Engineer (C, C++, Python, CXL, PCIE)

4 - 10 Years ExpOnsite - Hyderabad
PythonpytestCI/CDgtestC++C

Principal Design Verification Engineer

10 Years ExpOnsite - Bengaluru
System VerilogUVMPythonPerlEDA VerificationObject-Oriented DesignLinux

Senior Staff Engineer - Simulation Development

7 - 12 Years ExpOnsite - Pune
PythonC++System CFirmwareSoftware

Principal Switch Architect

8 - 10 Years ExpOnsite - Bengaluru
CC++PythonLayer 2Layer 3QOSmicro-architecture

Staff Engineer- Physical Design

4 - 8 Years ExpOnsite - Bengaluru
PerlTCLPythonCadence InnovusSynopsys FCVerilogVHDL

Senior Staff Engineer-Physical Design

8 - 12 Years ExpOnsite - Bengaluru
Cadence InnovusSynopsys FCPerlTCLPythonVerilogVHDL

Cyber Security Operations Analyst (Tier 2 SOC)

4 Years ExpHybrid - Hyderabad
IDS/IPSNGFWEDRSIEMvulnerability scannersHIDS/HIPSAV

Principal Engineer - DFT

13 - 15 Years ExpOnsite - Bengaluru
MBISTATPGvalidationSTAIP-DFXPost-Silicon bringupSCAN-Insertion

Windows Device Driver Developer

2 - 10 Years ExpOnsite - Pune
CStorage protocolsKernel ProgrammingWindows device driverUnix OSFCStorage Drivers