About
PricingContact
  • Company Industry

    Semiconductor Manufacturing

  • Headquarters

    5488 Marvell Lane, Santa Clara, - 95054, CA, US

About us

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

Funding

Self-funded (bootstrapped) company without external investments.

Current Openings at Marvell Technology

Engineer, Design Verification

5 Years ExpOnsite - Pune
IP verificationVerilogSystemVerilogUVMC/C++object-orientedcoverage analysis

Principal Engineer, Subsystem CoE Emulation

10 - 15 Years ExpOnsite - Bengaluru
SOC emulationvalidationDebughigh-speed protocolsemulation platformsScriptingMemory interfaces

Sr. Staff RTL Design Engineer - PCIe

8 Years ExpRemote - Bengaluru
RTL designSystemVerilogVerilogPCIECXLARMEDA tools

Staff CAD Engineer

6 Years ExpOnsite - Bengaluru
Cadence VoltusIR dropEM analysisASICSOCTCLPython

Sr. Principal Engineer, RTL ASIC Design

18 Years ExpOnsite - Hyderabad
ASIC designSoC ArchitectureRTL codingPerformance AnalysisDigital DesignARM Architecture

Senior Staff- IP RTL Design Engineer

8 - 14 Years ExpOnsite - Bengaluru
RTL designUCIeHBMSystemVerilogVerilogCDC/RDCSoC Architecture

Principal Engineer - Subsystem CoE Emulation

12 Years ExpOnsite - Bengaluru
SOC emulationhigh-speed interfacessecurity architectureDebuggingPythonPerlTCL

Staff Engineer • Custom Solutions Engineering - SoC

3 - 5 Years ExpOnsite - Pune
C/C++LinuxSOCFirmwarevalidationSATAUSB

Hardware & Silicon Validation Engg

3 - 5 Years ExpOnsite - Pune
CC++LinuxSOCvalidationDebugembedded

Package Design Staff to Senior Staff Engineer

FreshersOnsite - Bengaluru
package designC4BgaCadenceSI/PIthermal constraintsmechanical constraints

Senior Software Engineer (Linux Kernel - Networking)

3 - 5 Years ExpOnsite - Hyderabad
Linux kerneldevice driversMemory ManagementC programmingBMC protocolsFirmwareDebugging

Staff Engineer (L1, L2, L3 Testing, NOS/SDK testing, Python Automation)

3 - 10 Years ExpOnsite - Bengaluru
PythonNetworkingCI/CDTest automationGit

Principal Engineer - Verification / AMS / SerDes

14 Years ExpOnsite - Bengaluru
verificationSerdesAMSSystemVerilogUVMGLSpower-aware

Senior Staff/Principal SQA Engineer (Firmware/Embedded Testing, C/C++, Python/Bash)

7 - 15 Years ExpOnsite - Hyderabad
PythonC/C++BashSQAHardware debuggingEmbedded TestingGit

Package Layout Design Senior Staff Engineer

FreshersOnsite - Bengaluru
IC PackageC4BgaCadencepackage designSI/PIthermal constraints

Principal Validation Engineer

5 - 10 Years ExpOnsite - Pune
C/C++Embedded SWLinuxARMSOCDDRPCIE

Senior Staff Validation Engineer

FreshersOnsite - Bengaluru
C/C++ARM assembly64 bit Arm CPUFirmwareDebuggingSSDNAND

Analog Layout Staff Engineer

6 - 10 Years ExpOnsite - Bengaluru
mixed-signalCadence VirtuosoAnalog LayoutFinfetverificationEDA toolsautomation

Staff/Senior Staff Software Development Engineer (C/C++, Network Drivers, Data plane, Crypto, Compiler)

4 - 6 Years ExpOnsite - Bengaluru
C/C++NetworkingCryptoARMCompilers

Principal Technical Analyst – Supply Operations & Planning

10 Years ExpOnsite - Bengaluru
SQLETLKinaxisOracleAPISSupply PlanningData Integration

Senior Staff Engineer - Design Verification - Ethernet

8 Years ExpOnsite - Pune
VerilogSystem VerilogUVMDebuggingverificationEthernet

Memory Layout Staff Engineer

5 Years ExpOnsite - Bengaluru
Memory LayoutPhysical VerificationSemiconductorEDA toolsScriptinghigh-performancedesign rule

Senior Principal Engineer - RTL

20 Years ExpOnsite - Bengaluru
RTLVerilogSystem VerilogASICAIPythonIP integration

Senior Staff Engineer, RTL ASIC Design

8 Years ExpOnsite - Bengaluru
RTL designVerilogSystem VerilogASIC designpower analysisIP integrationPython

Senior Staff Engineer - AMS IP Verification

8 - 12 Years ExpOnsite - Bengaluru
SystemVerilogUVMSerdesAMSmixed-signalverificationFirmware

Principal Engineer- CAD/EDA Tools & Design Automation Engineer

12 Years ExpOnsite - Bengaluru
LinuxGitPythonJenkinsGitHub ActionsEDA toolsSynopsys VCS

Principal Engineer - Design Verification

12 Years ExpOnsite - Hyderabad
ARM-based SoCARM boot sequencesARM ArchitectureAMBA BusAXI-4CHIACE

Sr. Principal Design Verification Engineer (PCIe/CXL)

18 Years ExpOnsite - Bengaluru
UVMPCIECXLAXI-4VerilogSystemVerilogGit

Senior Principal Engineer, RTL ASIC Design

18 Years ExpOnsite - Bengaluru
RTLASIC designPythonTCLShellC++EDA tools

Frontend Infrastructure CAD/Tools Engineer

5 Years ExpOnsite - Bengaluru
PythonPerlEDA toolsGitGithubAI integrationLLM

Director Engineering

16 Years ExpOnsite - Hyderabad
RTLDVSOCemulationverificationprocessor architectureSOC components

Senior Staff Verification Engineer

8 Years ExpOnsite - Pune
SystemVerilogHDLUVMARM M series ProcessorsPerlShellPython

Principal Engineer (L2, L3 Protocol Development, Switching/Routing)

8 - 15 Years ExpOnsite - Bengaluru
C/C++PythonEthernet SwitchingRouting ProtocolsEmbedded SystemsLinuxnetwork software

Staff Engineer - Subsystem CoE Emulation

3 Years ExpOnsite - Bengaluru
SOC emulationPCIECXLEthernetDDRHBMPython

Senior Staff Engineer - Subsystem CoE Emulation

8 Years ExpOnsite - Bengaluru
SOC emulationvalidationDebugPCIECXLEthernetDDR

Senior Principal Engineer, Subsystem CoE Emulation

15 - 18 Years ExpOnsite - Bengaluru
SOC emulationPCIECXLEthernetDDRHBMPython

Senior Staff Engineer – PCIe EP Host Software

5 - 20 Years ExpOnsite - Hyderabad
PCIEGitNVMeCLinuxDMANetwork

Director, Engineering IT

15 Years ExpOnsite - Bengaluru
HPCEDA toolscloud platformsAWSGCPAzureITIL

Staff/Sr. Staff Field Applications Engineer (Networking)

6 - 10 Years ExpOnsite - Bengaluru
CC++L2 switchingRouting ProtocolsDebuggingcomputer networking

Senior SQA Manager (C. C++, Python, CXL, PCIE)

10 - 15 Years ExpOnsite - Hyderabad
PythonpytestC++CI/CDGDB

Principal SQA Engineer (L2, L3, Python Automation)

10 - 20 Years ExpOnsite - Bengaluru
PythonL2/L3NetworkingQA methodologiesTest PlanningLinux/UnixTraffic generators

Senior Staff Manager

12 - 18 Years ExpOnsite - Pune
VerilogSystemVerilogNOCAXIAHBSynopsysCadence

Sr. Staff Manager (Storage Protocol/ Fibre Channel Architecture & Development)

15 Years ExpOnsite - Pune
CLinuxWindowsStorage protocolsNVMeSCSIFC

Director, Design Verification

15 Years ExpOnsite - Hyderabad
emulationverification infrastructureIPsubsystemSOCSemiconductor VerificationChiplet

Staff/Sr. Staff Field Applications Engineer(Switching)

6 - 10 Years ExpHybrid - Bengaluru
CC++L2 switchingRoutingVLANSTPNetworking

Staff Engineer- PCIe Driver/ Linux Kernel Driver Development

4 Years ExpOnsite - Hyderabad
PCIECLinux kernelFirmwaredrivers

Sr Staff Firmware Engineer

5 - 10 Years ExpOnsite - Pune
C/C++Cryptographic technologiesJTAGPCIE protocolSMBUSARM-based CPU architecturesIPsec accelerators

Director, IT Enterprise Applications & Platforms

15 Years ExpOnsite - Bengaluru
ERPIntegration PlatformsServiceNowCI/CDDevOpsenterprise architecturePlatform Engineering

Staff/Sr. Staff Field Applications Engineer

7 - 12 Years ExpOnsite - Bengaluru
C languageLinuxdriversDebuggingFirmwareWindows BIOSstorage ASICs

Staff Verification Engineer- PCIe/UALink/CXL

3 - 5 Years ExpOnsite - Bengaluru
System VerilogUVMVerilogPythonTCLPerlCXL

Design Verification Principal Engineer

12 Years ExpOnsite - Bengaluru
SoC verificationARM ArchitectureUVM testbenchC codingEthernetPCIEDebugging

Staff/ Senior Staff QA Engineer (C, C++, Python, CXL, PCIE)

4 - 10 Years ExpOnsite - Hyderabad
PythonpytestC++CGithubJenkins

Principal Design Verification Engineer

10 Years ExpOnsite - Bengaluru
System VerilogUVMPythonPerlEDA VerificationObject-Oriented DesignLinux

Senior Staff Engineer - Simulation Development (System C/VDK)

7 - 12 Years ExpOnsite - Pune
PythonC++System CFirmwareSimulationSOCArchitecture

Windows Device Driver Developer (C, Kernel Programming, Storage protocols)

5 - 10 Years ExpRemote - Pune
CStorage protocolsKernel ProgrammingAPI LibrariesLinuxWindowsdevice drivers

Senior Principal Security Engineer– HSM & Cryptography

17 Years ExpRemote - Bengaluru
HSMAgileC++CryptographyDebuggingCCI/CD

Security Developer (C, Linux, System Security, Embedded programming)

8 - 12 Years ExpOnsite - Hyderabad
CLinuxMultithreadingstatic analysisMultiprocessorAgile

Principal Switch Architect

8 - 10 Years ExpOnsite - Bengaluru
CC++PythonLayer 2Layer 3QOSmicro-architecture

Staff Engineer- Physical Design

4 - 8 Years ExpOnsite - Bengaluru
PerlTCLPythonCadence InnovusSynopsys FCVerilogVHDL

Senior Staff Engineer-Physical Design

8 - 12 Years ExpOnsite - Bengaluru
Cadence InnovusSynopsys FCPerlTCLPythonVerilogVHDL

Cyber Security Operations Analyst (Tier 2 SOC)

4 Years ExpHybrid - Hyderabad
IDS/IPSNGFWEDRSIEMvulnerability scannersHIDS/HIPSAV

Principal Engineer - DFT

13 - 15 Years ExpOnsite - Bengaluru
MBISTATPGvalidationSTAIP-DFXPost-Silicon bringupSCAN-Insertion

Windows Device Driver Developer

2 - 10 Years ExpOnsite - Pune
CStorage protocolsKernel ProgrammingWindows device driverUnix OSFCStorage Drivers