About
PricingContact
  • Company Industry

    Semiconductor Manufacturing

  • Headquarters

    2625 Augustine Drive, Santa Clara, - 95054, California, US

About us

The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
  • Funding Round/Series

    Series F

  • Funding Amount

    $ 175M

  • Latest Funding Date

    3, 2022

Current Openings at SiFive

Senior Design Verification Infrastructure Engineer

3 Years ExpOnsite - Bengaluru
System VerilogUVMdesign verificationScalaChiselPython

Staff Engineer, Physical Design

8 Years ExpOnsite - Bengaluru
Physical DesignPPAEDA toolssynthesisFloorplanningRTLImplementation

Staff Engineer, Physical Design

8 Years ExpOnsite - Bengaluru
Physical DesignclockingInterconnectTiming ClosureVLSI DesignEDA toolsCircuit Design

Senior Customer Release Engineer

4 Years ExpOnsite - Bengaluru
PythonRelease workflowsJSONYAMLAssemblyC++Linux

Staff / Sr. Staff Engineer DV

7 Years ExpOnsite - Bengaluru
UVMPythonpower simulationpower managementScript Writing

Engineer I

1 Years ExpOnsite - Bengaluru
Digital ElectronicsVLSI DesignC/C++JavaPythonVerilogSystem Verilog

Staff Engineer, Physical Design

7 Years ExpOnsite - Bengaluru
Physical DesignCPUpower managementPPARTLGDSIIautomation

Senior Staff Verification Engineer

10 Years ExpOnsite - Bengaluru
SystemVerilogUVMRISC-VPythonC/C++AXIDebugging

Senior Engineer, R2G Methodology and PD execution

4 Years ExpOnsite - Bengaluru
Physical Designdigital implementationTCLPythonpowerperformanceArea

Senior IP Verification Engineer

3 Years ExpOnsite - Bengaluru
System VerilogUVMPythonC/C++AXIAHBCPU

Staff Engineer - Design Verification

7 Years ExpOnsite - Hyderabad
design verificationCPU verificationSystemVerilogUVMarchitecture validationtest plansfunctional coverage

Senior Customer Support Engineer

4 Years ExpOnsite - Bengaluru
Physical DesignDebuggingDocumentationCollaborationPower PerformanceScriptingEDA

Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)

1 Years ExpOnsite - Hyderabad
System VerilogUVMPythonBashPerlArchitectureverification

Staff Engineer - DV

7 - 12 Years ExpOnsite - Bengaluru
System VerilogUVMPythonCPU architectureTest writingtest planAXI

CPU Design Verification Engineer

5 Years ExpOnsite - Hyderabad
System VerilogUVMverificationDebugmicro-architecturetestbenchDesign

Staff Engineer - Formal Verification

8 Years ExpOnsite - Bengaluru
Formal Verificationdigital hardwareFormal AbstractionVC FormalJaspergoldVHDLVerilog

Engineer 1

1 Years ExpOnsite - Hyderabad
VerilogPythonBashDebuggingPerlCPU architectureautomation

Staff Engineer

7 Years ExpOnsite - Ahmedabad
SystemVerilogUVMDebuggingprotocolASICSOCverification

NoC Design Verification Engineer

4 Years ExpOnsite - Ahmedabad
design verificationSystemVerilogUVMassertionscoverageCachememory fabrics

Staff Design Verification Infrastructure Engineer

FreshersOnsite - Bengaluru
design verificationSystem VerilogUVMChiselScala

Staff Design Verification Infrastructure Engineer

7 Years ExpOnsite - Bengaluru
design verificationSystem VerilogUVMScalaChisel

Staff Engineer, Low Power Verification & Formal Equivalence

7 Years ExpOnsite - Bengaluru
low powerUPFFormal EquivalenceLogical Equivalencepower managementverificationStatic Power

Senior Engineer, PPA Analytics & CAD

4 Years ExpOnsite - Bengaluru
PythonTCLSQLGrafanaAIdigital ASIC

Senior Staff Engineer, Physical Design - NoC

10 Years ExpOnsite - Bengaluru
NOCPhysical DesignPPA optimizationRTLsynthesisCadenceHierarchical P&R

Staff Engineer, Physical Design - Caches

7 Years ExpOnsite - Bengaluru
Physical DesignRTLGDSIISRAMPPAsynthesisPNR

Senior Design Verification Engineer

5 Years ExpOnsite - Ahmedabad
verificationSystemVerilogUVMDebuggingScriptingDesignArchitectural

Product Power Engineer

5 Years ExpHybrid - Bengaluru
power benchmarkingpower analysispower modelingArchitectureLogic Designcircuit analysisCPU design

Senior Staff Engineer, Static Timing Analysis (STA) Lead

10 Years ExpOnsite - Bengaluru
PrimetimeStatic Timing Analysis3nmPhysical DesignSDCClock Tree SynthesisVLSI

Sr. Design Verification Infrastructure Engineer

5 Years ExpOnsite - Bengaluru
scripting languageBuild system architectureWake language

Power Infrastructure Engineer

5 Years ExpOnsite - Bengaluru
power benchmarkingpower analysispower modelingcomputer architectureCPU designsRTLASIC