FPGA design & development
RTL design (Register Transfer Level)
Hardware description languages (HDL): Verilog, VHDL
SystemVerilog (advanced verification)
Digital logic design
Finite State Machines (FSM)
Timing analysis & closure
Static timing analysis (STA)
Clock domain crossing (CDC)
Reset domain crossing (RDC)
Synthesis & place-and-route
FPGA toolchains: Xilinx Vivado, Intel Quartus
Simulation tools: ModelSim, QuestaSim
Testbench development
Functional verification
UVM (Universal Verification Methodology)
FPGA design & development
RTL design (Register Transfer Level)
Hardware description languages (HDL): Verilog, VHDL
SystemVerilog (advanced verification)
Digital logic design
Finite State Machines (FSM)
Timing analysis & closure
Static timing analysis (STA)
Clock domain crossing (CDC)
Reset domain crossing (RDC)
Synthesis & place-and-route
FPGA toolchains: Xilinx Vivado, Intel Quartus
Simulation tools: ModelSim, QuestaSim
Testbench development
Functional verification
UVM (Universal Verification Methodology)
FPGA design & development
RTL design (Register Transfer Level)
Hardware description languages (HDL): Verilog, VHDL
SystemVerilog (advanced verification)
Digital logic design
Finite State Machines (FSM)
Timing analysis & closure
Static timing analysis (STA)
Clock domain crossing (CDC)
Reset domain crossing (RDC)
Synthesis & place-and-route
FPGA toolchains: Xilinx Vivado, Intel Quartus
Simulation tools: ModelSim, QuestaSim
Testbench development
Functional verification
UVM (Universal Verification Methodology)