• Founded in

    2017

  • Company Industry

    Semiconductor Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
  • Funding Round/Series

    Series C

  • Funding Amount

    $ 50M

Current Openings at Astera Labs

Prinicipal Software QA Engineer

8 Years ExpOnsite - Bengaluru
PCIEPythonautomationManual Testingprotocolstest strategiesPerformance Testing

Principal Digital Design Engineer

12 Years ExpOnsite - Bengaluru
RTL developmentsynthesisTiming ClosureSystem VerilogVerilogPythonPerl

Principal DFT Engineer (Design for Test)

12 Years ExpOnsite - Bengaluru
Chip DesignVerilogSystem VerilogverificationUVM MethodologyATPG ToolsScan insertion tools

Analog Mixed-Signal IC Layout Lead

5 Years ExpRemote
Cadence VirtuosotapeoutCadence SKILLhigh-speed IC layoutBiCMOS layoutlayout extractionEMIR layout

Principal SQA Engineer

8 Years ExpOnsite - Bengaluru
PythonPCIE protocolScriptingAutomation TestingPerformance TestingInteroperability testingstress tests

Lead Engineer, Formal Verification

7 Years ExpOnsite - Bengaluru
Formal Verificationdesign verificationSystem VerilogPythonEDA toolsassertionstest plans

Principal, Firmware Engineer

8 Years ExpOnsite - Bengaluru
FirmwareSOCCC++PythonRTOSMQX

Lead Software QA Engineer

6 Years ExpOnsite - Bengaluru
PythonPCIEautomationtestingScriptingSignal Integrityvalidation

Senior Digital Design Engineer-CXL/PCIe

8 Years ExpOnsite - Bengaluru
RTL developmentTiming Closuremicro-architectureblock-level designPCIESystem Verilogdesign verification

Principal STA Engineer - DFT Focus

6 - 8 Years ExpOnsite - Bengaluru
ASICDFTTiming AnalysisPrimetimeTiming Closuretiming constraintsScripting

Senior Physical Design Engineer

3 Years ExpOnsite - Bengaluru
synthesistimingExtractionplace and routeCadenceSystem VerilogDft tools

Principal Design Verification Engineer - CXL/PCIe

8 Years ExpOnsite - Bengaluru
PCIECXLUVMassertionsverification planscoverage data

Senior Firmware Engineering

5 Years ExpOnsite - Bengaluru
SOCRTOSCPythonMQXBMCHW-SW

Senior Digital Design Engineer - SOC

5 Years ExpOnsite - Bengaluru
RTL developmentsynthesisTiming ClosureSystem VerilogUVM-based verificationprocessor IPI2C/SPI/UART

Senior Design Verification Engineer - CXL/PCIe

5 Years ExpOnsite - Bengaluru
PCIECXLUVMassertionssimulatorsRegressionVIP