• Founded in

    2017

  • Company Industry

    Semiconductor Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
  • Funding Round/Series

    Series C

  • Funding Amount

    $ 50M

Current Openings at Astera Labs

Principal Emulation Engineer

10 Years ExpOnsite - Bengaluru
emulationtest benchesASIC developmentfunctional verificationSystem-level testsC++verification lifecycle

Analog Mixed-Signal IC Layout Lead

8 Years ExpRemote
Analog icCadence VirtuosoBicmostapeoutlayout extractionparasitic analysisEMIR

Principal Physical Design Engineer

10 Years ExpOnsite - Bengaluru
synthesisplace and routeTiming AnalysisPhysical VerificationCadenceSystem VerilogScripting

Lead Physical Design Engineer

8 Years ExpOnsite - Bengaluru
synthesisplace and routeTiming AnalysisPhysical VerificationCadenceSystem VerilogDft tools

Principal Firmware Engineer

5 Years ExpOnsite - Bengaluru
SOCCPythonGithubFirmwareSDKGCC

Lead Firmware Engineer

5 Years ExpOnsite - Bengaluru
SOCFirmwareC++C

Senior Firmware QA Engineer

4 Years ExpOnsite - Bengaluru
PythonSignal IntegrityPCIE protocolAutomation Testingvalidationtest strategiesManual Testing

Lead Physical Design Engineer

7 Years ExpOnsite - Bengaluru
synthesisplace and routeCTSPhysical VerificationCadenceSystem Verilogextraction timing

Principal Digital Design Engineer

12 Years ExpOnsite - Bengaluru
RTL developmentsynthesisTiming ClosureSystem Verilogprocessor IPDMA enginesUVM-based verification

Lead Engineer, Formal Verification

7 Years ExpOnsite - Bengaluru
Formal Verificationdesign verificationSystem VerilogPythonEDA toolsassertionsPerl

Lead Firmware QA Engineer

6 Years ExpOnsite - Bengaluru
PCIE protocolPythonFunctional TestingPerformance TestingInteroperability testingAutomation TestingSignal Integrity

Senior Digital Design Engineer-CXL/PCIe

8 Years ExpOnsite - Bengaluru
RTL developmentTiming ClosurePCIESystem Verilogsynthesisprocessor IPUVM