• Founded in

    2017

  • Company Industry

    Semiconductor Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
  • Funding Round/Series

    Series C

  • Funding Amount

    $ 50M

Current Openings at Astera Labs

Senior System Validation Engineer

4 Years ExpHybrid - Visakhapatnam
Pythonhigh-speed protocolsBench automationProtocol AnalyzersSilicon/System validationin-circuit debuggersCPU-based tool suites

Principal System Validation Engineer

8 Years ExpRemote
CXLPCIEPythonhigh-speed protocolsNVMeEthernetDebug Experience

Lead DFT Engineer (Design for Test)

4 Years ExpOnsite - Bengaluru
Chip DesignVerilogSystem VerilogUVM MethodologyATPG ToolsScan insertionScripting

Principal Emulation Engineer

10 Years ExpOnsite - Bengaluru
emulationC++ASICCodingverification testbench

Analog Mixed-Signal IC Layout Lead

8 Years ExpRemote
Cadence Virtuosotapeoutlayout extractionparasitic analysisEMIRBiCMOS layoutDRC

Principal Physical Design Engineer

10 Years ExpOnsite - Bengaluru
synthesisplace and routeTiming AnalysisPhysical VerificationCadenceCTSSynopsys

Principal Firmware Engineer

5 Years ExpOnsite - Bengaluru
SOCCPythonFirmwareC++SDKsHW-SW

Principal Digital Design Engineer

12 Years ExpOnsite - Bengaluru
RTL developmentsynthesisTiming ClosureSystem Verilogprocessor IPDMA enginesI2C/SPI

Lead Firmware QA Engineer

6 Years ExpOnsite - Bengaluru
PythonSignal IntegrityPCIEScriptingautomationManual TestingProtocol validation

Senior Digital Design Engineer-CXL/PCIe

8 Years ExpOnsite - Bengaluru
RTL developmentTiming ClosurePCIESystem Verilogsynthesisprocessor IPmicro-architecture