About
PricingContact
  • Founded in

    2017

  • Company Industry

    Semiconductor Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
  • Funding Round/Series

    Series C

  • Funding Amount

    $ 50M

Current Openings at Astera Labs

Principal Physical Design Engineer

8 Years ExpOnsite - Ahmedabad
synthesisplace and routeCTSTiming AnalysisPhysical VerificationCadenceSynopsys

Principal Logic Design Engineer

10 Years ExpOnsite - Bengaluru
RTLmicroarchitectureSystemVerilogVerilogPCIEEthernetCXL

Silicon Design Architect

20 Years ExpOnsite - Bengaluru
IP architectureDigital Designcomputer architectureSoC Designmicroarchitecturememory systemsInterconnects

DFT Engineer

5 Years ExpOnsite - Bengaluru
VerilogSystemVerilogRTL codingsynthesisTiming ClosureCDClow-power design

Principal Logic Design Engineer - UALink IP/Subsystem

10 - 15 Years ExpOnsite - Bengaluru
RTLmicroarchitectureInterconnectsSystemVerilogCDCHardware Design

Lead Logic Design Engineer

6 - 10 Years ExpOnsite - Bengaluru
RTL designSystemVerilogVerilogPCIECXLEthernetUCIe

Tech Lead, STA

6 - 14 Years ExpOnsite - Hyderabad
Static Timing AnalysisPrimetimeClock-domain crossingScriptingED-EDA vendor engagements

Senior STA Engineer

6 Years ExpOnsite - Ahmedabad
Static Timing AnalysisSynopsys PrimeTimeCadence tempusSDC constraintsASIC/SoC DesignSTAMCMM/MMMC analysis

Lead Logic Design for UALink IP/Subsystem Engineer

6 - 10 Years ExpOnsite - Bengaluru
RTLmicroarchitectureSystemVerilogDebuggingHigh-Speeddata movementflow control

Firmware Engineer Tech Lead

5 Years ExpOnsite - Bengaluru
CC++PythonPCIESOCSDKGithub

Tech Lead– Verification Methodology/CAD

6 - 12 Years ExpOnsite - Bengaluru
verificationCADautomationPythonTCLSystemVerilogUVM

Principal Design Verification Engineer

12 Years ExpRemote - Visakhapatnam
PCIECXLUVMassertionsVerification IPtest plansSimulation

Tech Lead, Formal Verification

5 - 10 Years ExpOnsite - Bengaluru
SystemVerilogSVAPythonPerlTCLFormal VerificationAbv

SoC Design Director

15 Years ExpOnsite - Bengaluru
PCIEDigital DesignRTL designVerilogSystemVerilogASIC developmentDFT

IP Design Director

15 Years ExpOnsite - Bengaluru
PCIEUALinkEthernetDigital DesignIP developmentProgram Managementmicroarchitecture

Soc Design Verification Director

20 Years ExpHybrid - Bengaluru
SoC verificationHSIOUVMassertionscoverage analysisIntegrationDebugging