• Founded in

    2021

  • Company Industry

    Computer Hardware Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise

Funding

Self-funded (bootstrapped) company without external investments.

Current Openings at Rivos Inc.

Silicon Verification - Intern

FreshersOnsite - Bengaluru
SystemVerilogC/C++verification methodologiesdigital logic designCPU/SOC architecturesimulatorswaveform viewers

Silicon Logic Formal Verification

FreshersHybrid - Bengaluru
Formal VerificationTemporal Assertionmodel checking

Floating Point Logic Design

FreshersHybrid - Kannur
System VerilogIEEE-754FMA operationsC++ programmingLogic DesignC

Data Parallel Accelerator Post-Silicon Performance Lead

5 - 12 Years ExpHybrid - Kannur
PythonPerformance countersGP-GPU architectureML/DL workloadsSIMT processingC/C++microarchitecture

GPGPU runtime software engineer

FreshersOnsite - Kannur
C++RustC

GPGPU SW and HW design validation engineer

FreshersHybrid - Kannur
CC++

Deep Learning Libraries engineer

3 Years ExpHybrid - Kannur
C++Parallel programmingcomputer architectureDeep LearningCPyTorch

SOC Physical Design Verification Engineer

FreshersHybrid - Bengaluru
TCLPythonSiemens Calibre

SOC Static Timing Analysis Engineer

FreshersOnsite - Bengaluru
PythonTCLTiming ClosureASIC timing constraintstiming EDA toolsdeep-sub micron processescsh/bash

SOC Design Verification

FreshersHybrid - Bengaluru
SystemVerilogC/C++DDR memoryEthernetPCIEVerilogDigital Logic

SOC Physical Design

FreshersHybrid - Bengaluru
synthesisPlace & RouteUnixPerlPythonVerilogSystemVerilog

Silicon Logic Formal Verification

FreshersHybrid - Bengaluru
RISC-Vmodel checkingformal specification

Senior Memory Design Engineer

8 - 15 Years ExpHybrid - Bengaluru
PPA analysisequivalence checkinglow power designtimingCircuit DesignSimulationcharacterization

Logic Equivalence Check (LEC) Engineer

5 - 8 Years ExpHybrid - Bengaluru
TCLPythonPerlConformal LECFormalityABORT/NEQ debugging

DFT Engineer

FreshersHybrid - Bengaluru
Verilogdigital logic designMicroprocessorDFT architectureCPU architecturedebug featuremicroarchitecture

CPU Design Verification

FreshersHybrid - Bengaluru
SystemVerilogCPU architecturedigital logic designC/C++verification methodologies

Analog Mixed Signal Design Verification

5 Years ExpHybrid - Bengaluru
SystemVerilogUVMverification

Accelerator Design Verification

5 Years ExpHybrid - Bengaluru
System VerilogC++Pythoncomputer architecture