Rivos Inc.

  • Founded in

    2021

  • Company Industry

    Computer Hardware Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise

Funding

Self-funded (bootstrapped) company without external investments.

Current Openings at Rivos Inc.

Silicon Verification - Intern

FreshersOnsite - Bengaluru
SystemVerilogC/C++verification methodologiesPythonTCLFormal Verification
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Silicon Logic Formal Verification

FreshersHybrid - Bengaluru
Temporal Assertionmodel checking
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Floating Point Logic Design

FreshersHybrid - Kannur
System VerilogIEEE-754CsimulatorsFmawaveform debugging toolsC++
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Data Parallel Accelerator Post-Silicon Performance Lead

5 - 12 Years ExpHybrid - Kannur
PythonC/C++Performance countersEmbedded SystemsGP-GPU architectureML/DL workloadsSIMT processing
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SOC Physical Design Verification Engineer

FreshersHybrid - Bengaluru
TCLPythonSiemens Calibre
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SOC Static Timing Analysis Engineer

FreshersOnsite - Bengaluru
ASIC timingTCLPythonEDA toolsdeep-sub micron processesTiming ClosureScripting languages
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SOC Design Verification

FreshersHybrid - Bengaluru
SystemVerilogC/C++verification methodologiesPythonTCL
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SOC Physical Design

FreshersHybrid - Bengaluru
PerlPythonVerilogUnixTCLsynthesisPlace & Route
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Silicon Logic Formal Verification

FreshersHybrid - Bengaluru
model checkingFormal VerificationRISC-VTheorem Provers
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Senior Memory Design Engineer

8 - 15 Years ExpHybrid - Bengaluru
PPA analysisequivalence checkinglow power designtimingCircuit DesignSimulationcharacterization
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Logic Equivalence Check (LEC) Engineer

5 - 8 Years ExpHybrid - Bengaluru
TCLPythonConformal LECPerlFormality
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DFT Engineer

FreshersHybrid - Bengaluru
digital logic designMicroprocessorDFT architectureCPU architectureVerilogSystemVerilog
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CPU Design Verification

FreshersHybrid - Bengaluru
SystemVerilogC/C++verification methodologiessimulatorswaveform viewersbuild and run automationcoverage collection
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Analog Mixed Signal Design Verification

5 Years ExpHybrid - Bengaluru
SystemVerilogUVMverification
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Accelerator Design Verification

5 Years ExpHybrid - Bengaluru
System VerilogC++Pythoncomputer architecture
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