Rivos Inc.

  • Founded in

    2021

  • Company Industry

    Computer Hardware Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise

Funding

Self-funded (bootstrapped) company without external investments.

Current Openings at Rivos Inc.

Silicon Verification - Intern

FreshersOnsite - Bengaluru
SystemVerilogC/C++verification methodologiesFormal Verification
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Silicon Logic Formal Verification

FreshersHybrid - Bengaluru
Temporal Assertionmodel checking
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Floating Point Logic Design

FreshersHybrid - Kannur
System VerilogIEEE-754FMA operationsCC++
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Data Parallel Accelerator Post-Silicon Performance Lead

5 - 12 Years ExpHybrid - Kannur
PythonC/C++Performance countersGP-GPU architectureSIMT processingprofiling techniquesBottleneck analysis
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SOC Physical Design Verification Engineer

FreshersHybrid - Bengaluru
TCLPythonSiemens CalibrePhysical Verificationdeep sub-micron
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SOC Static Timing Analysis Engineer

FreshersOnsite - Bengaluru
TCLPythondeep-sub micron processesASIC timing constraintsTiming ClosureEDA toolscsh/bash
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SOC Design Verification

FreshersHybrid - Bengaluru
SystemVerilogC/C++verification methodologiesdigital logic designCPU/SOC architecturemicroarchitecture
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SOC Physical Design

FreshersHybrid - Bengaluru
synthesisPlace & RouteAnalysisverification CAD toolsUnixPerlPython
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Silicon Logic Formal Verification

FreshersHybrid - Bengaluru
Formal Verificationtemporal assertion propertiesmodel checking tools
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Senior Memory Design Engineer

8 - 15 Years ExpHybrid - Bengaluru
PPA analysisequivalence checkinglow power designtimingCircuit DesignSimulationcharacterization
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Logic Equivalence Check (LEC) Engineer

5 - 8 Years ExpHybrid - Bengaluru
TCLPythonConformal LECPerlFormality
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DFT Engineer

FreshersHybrid - Bengaluru
VerilogSystemVerilogMBISTscan dumpMemory DumpDFT architectureCPU architecture
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CPU Design Verification

FreshersHybrid - Bengaluru
SystemVerilogC/C++verification methodologiesdigital logic designCPU architecture
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Analog Mixed Signal Design Verification

5 Years ExpHybrid - Bengaluru
SystemVerilogUVMverification
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Accelerator Design Verification

5 Years ExpHybrid - Bengaluru
System VerilogC++Pythoncomputer architectureCPU/GPU/Accelerator DV
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