Rivos Inc.

  • Founded in

    2021

  • Company Industry

    Computer Hardware Manufacturing

  • Headquarters

    Santa Clara, - 95054, CA, US

About us

Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise

Funding

Self-funded (bootstrapped) company without external investments.

Current Openings at Rivos Inc.

Data Parallel Accelerator Post-Silicon Performance Lead

5 - 12 Years ExpHybrid - Kannur
C++PythonPerformance countersEmbedded SystemsGP-GPU architectureML/DL workloadsSIMT processing
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Custom CAD Back End

5 - 8 Years ExpHybrid - Kannur
Virtuosocustom compilerTotemSpectreSPICEVCSVoltus-fi
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Senior Member of Technical Staff

2 Years ExpHybrid - Kannur
PCIE protocolSystem VerilogPerlPythonTcl/TkUVCMVerilog-OVM Methodology
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GPGPU runtime software engineer

FreshersOnsite - Kannur
C++Rust組込みLinux
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GPGPU SW and HW design validation engineer

FreshersHybrid - Kannur
CC++Cuda Programming
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Deep Learning Libraries engineer

3 Years ExpHybrid - Kannur
CC++Parallel programmingcomputer architectureDeep Learning
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SOC Static Timing Analysis Engineer

FreshersOnsite - Bengaluru
PythonASICTCLEDA toolscsh/bashPOCVIR-STA
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SOC Design Verification

FreshersHybrid - Bengaluru
SystemVerilogC/C++verification methodologiessimulatorswaveform viewers
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SOC Physical Design

FreshersHybrid - Bengaluru
synthesisPlace & RoutetimingfloorplanclockingElectrical analysispower
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Silicon Power

FreshersHybrid - Bengaluru
VerilogSystemVerilogPythonPerlTCLASIC
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Silicon Logic Formal Verification

FreshersHybrid - Bengaluru
model checkingFormal Verification
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Silicon DFT - Intern

FreshersHybrid - Bengaluru
VerilogDFTJTAG
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Senior Memory Design Engineer

8 - 15 Years ExpHybrid - Bengaluru
PPA analysisequivalence checkinglow power designtimingCircuit DesignSimulationcharacterization
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Python CAD Developer

3 - 6 Years ExpOnsite - Bengaluru
PythonDigital Design
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Logic Equivalence Check (LEC) Engineer

5 - 8 Years ExpHybrid - Bengaluru
TCLPythonPerlConformal LECFormalityABORT/NEQ
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DFT Engineer

FreshersHybrid - Bengaluru
VerilogSystemVerilogdigital logic designMicroprocessordebug featureDFT architectureCPU architecture
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CPU Design Verification

FreshersHybrid - Bengaluru
SystemVerilogC/C++CPU architecture
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Analog Mixed Signal Design Verification

5 Years ExpHybrid - Bengaluru
SystemVerilogUVMverification
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Accelerator Design Verification

5 Years ExpHybrid - Bengaluru
System VerilogC++Pythoncomputer architectureverification methodologies
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